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CY28378
...................... Document #: 38-07519 Rev. ** Page 17 of 21
Switching Waveforms
Note:
6. Device is not affected, VTT_PWRGD# is ignored.
FS_A, FS_B
VTT_PWRGD#
PWRGD_VRM
VDD Clock Gen
Clock State
Clock Outputs
Clock VCO
0.2-0.3mS
Delay
State 0
State 2
State 3
Wait for
VTT_PWRGD#
Sample Sels
Off
On
State 1
Device is not affected,
VTT_PWRGD# is ignored
Figure 6. VTT_PWRGD# Timing Diagram[6]
VTT_PWRGD# = Low
Delay
>0.25mS
S1
Power Off
S0
VDDA = 2.0V
Sample
Inputs straps
S2
Normal
Operation
Wait for 1.146ms
Enable Outputs
S3
VTT_PWRGD# = toggle
VDDA = off
Figure 7. Clock Generator Power-up/Run State Diagram
Duty Cycle Timing
t1B
(Single-ended Output)
t1A
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